科技惠泽天下 · 创芯以本为源

Outline

TSMC Integration Technologies

TSMC 3DFabric

New Transition

Outline

Integration Technologies

InFO_B(Bottom Only) for Mobile AP

INFO-R/oS for HPC Chiplet Integration

InFO_oS Envelope Growth for HPC Applications

InFO-L/LSI for UH-Bandwidth Chiplet Integration

INFO for Ultra High Performance Compute Systems

SoIS(System on Integrated Substrate)

SoIS Interconnect Performance

SoIS Design Rule & Power Performance

SoIS Reliability Evaluation

Key Advantages of InFO_SoW

Benchmark MCM vs InFO_SoW

Electrical Characterization

InFO_SoW Summary

CoWoS-S Technology

CoWoS-S Rapid Progress

CoWoS-S & Flip-chip CPI Comparison

Leading CoWoS Solutions for HPC

Chiplets Integration Reduces System Cost/function

CoWoS-S STAR(STandard APchitecture)

CoWoS-L for Heterogeneous Integration

3D Chip Stacking-SoIC

SoIC Development Direction

Inter-chip Interconnect Scaling Roadmap

Sub-um CoW Interconnect Feasibility

SoIC “Envelop Growth”

Outline

Thermal Solution Enhancement

Integrated Si Micro-Cooler(ISMC) for Ultra-HPC

Cooling Performance Benchmark

ISMC Summary

The Need for SiPh

Evolution of SiPh Package

Photonic Engine Integration Schemes
Electrical Interface(1/2) – Parasitics and PDN impedance

Electrical Interface(2/2) – Power Consumption

Opticala Interface: Overview

Optical Interface: GC and EC with COUPE

Summary